The present invention is directed to a digital logic circuit and, more particularly, to a master-slave flip-flop with low power consumption.
Master-slave flip-flops are widely used in digital logic circuits. Typically a master-slave D flip-flop has two gated latches connected in series and driven by a two-phase clock signal. The master latch registers the value of the input signal at the trailing edge of a first phase of the clock signal, which is the active clock edge for the master latch. The slave latch registers the value of the output signal from the master latch at the trailing edge of the following, opposite phase of the clock signal, which is the active clock edge for the slave latch.
Since a large number of flip-flops may be used in a typical integrated circuit (IC), the power consumption of the flip-flops can be significant. Various techniques have been used to reduce this power consumption. However, most of these techniques have the disadvantages of increasing circuit area and/or leading to performance penalties such as increased set-up or hold times, clock glitches and risk of unstable operation.
Thus, it would be advantageous to be able to reduce power consumption of flip-flops in an IC while avoiding some or all of these disadvantages.